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1 p/n: pm0743 rev. 2.5b, aug. 18, 2000 MX88L60 brief features ? power - 3.3v with power saving control ? image sensor interface - 8-bit to 10-bit resolution for digital image raw data input - support imager with resolution up to svga (800x592)with windowing mode or random-access control - support universal serial interface for various ccd and cmos sensors * ccd sensor: sony , sharp , and panasonic * cmos sensor: hyundai, hp, vlsi vision (vvl), photobit, biomorphic, tasc, etc. ? image processing unit - complete image processing functions: * rgb bayer cfa color interpolation * black reference * defect concealment * flare and black level correction * brightness and contrast control * edge enhancement * color correction * gamma correction * rgb to yuv color space conversion * color saturation control * false color suppression * image sub-sampling - programmable 5(h) x 5(v) zones with programmable size for image statistical calculation to facilitate automatic exposure control and automatic white balance - support focus-assisting signaling control (with melody ic interface) ? video compression unit - high quality and high performance proprietary compression algorithm for live video capture and transferring * 30 fps for cif (352x288) * 10~15 fps for vga (640x480) ? memory control interface - support both edo dram (256kx16) x1 or sdram (1mx16) x1 or x2 - support nand-type flash memory (8mb,16mb,32mb,64mb) x1 or x2 - support serial flash memory (mx25l4004, 4mb) x1, x2,x3 or x4 - support compact flash card and smart media card. - support ndr-type flash memory (16mb,32mb,64mb) - support eeprom for sensor information - support flash memory format function, controlled by pc software ? pc interface - high speed usb interface with embedded transceiver - uart interface with external transceiver, for best backward compatibility ? portable mode additional features - embedded 8051 micro-controller - support external rom code storage at flash memory or eprom - embedded real-time-clock (rtc) for time stamp * adjusted by pc software * on-system programming capability at portable mode - support monochrome tn lcd for information display. the logos include: * date * time * number of pictures left: 2 or 3 digits * flash light status: on/off/auto * self timer: on, off, and flash when push the snap shot button * battery status: high, low, and empty * continuous shots: on and off * quality (compression rate): best, better, good (total 8 classes actually) * image size: full, 1/2 - support self timer function - support melody ic for singling control when * initialization * self timer * snap shot * low battery * failure shot - support flashlight charge control ? miscellaneous - 48 mhz system clock operation - dedicated sensor clock input(optional) - built in 27 general-purpose i/o pins - 160 pin lqfp dual-mode pc camera controller
2 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 pin configuration general description the MX88L60 is a general-purpose controller for dual- mode (tethered and portable) pc cameras and toy cameras. the MX88L60 contains all the necessary hardware supports, like image sensor control and interface, image capture and processing, proprietary video compression, memory control, usb and uart interface, embedded micro-controller and general-purpose i/os. with the intensive hardware and associated software supports, it is an ideal solution for a tethered digital video camera, which can capture real-time live video for entertainment or videoconference applications. for still image capture, the MX88L60 can also function as a controller for low-cost digital still camera (dsc) or toy camera. with flash memory interface support and power- saving control, it can make the system work on battery power for portable purpose. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 gnd p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 gnd vdd p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 gnd vdd d+ d- gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 xclpdm xrs gnd xshd xshp xsg2 xsg1 xv3/hro xv2/fro xv1/hri xv0fri xsub h2 h1 rg fq7 fq6 fq5 fq4 fq0 vdd fq1 fq2 fq3 gnd vdd gnd fceb_b fcea_b fre_b frb_b fcle fale fwe_b fwp_b da4 da5 da6 da7 da8 vdd gnd clk32ki clk32ko gnd dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 vdd gnd dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dwe_b dcas_b dras_b sdcsa_b sdcsb_b sdcke vdd sd_clk gnd doe_b dbank da10 da0 da1 da2 da3 da9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 psen_b pale rst_b ea clk48o clk48i vdd gpio 25 gpio 24 gpio 23 gpio 22 gpio 21 clksno clksn gpio 20 gpio 19 gpio 18 gpio 17 gnd gpio 16 gpio 15 gpio 14 gpio 13 gpio 12 gnd vdd sd9 sd8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 adck vdd pblk xclpob MX88L60
3 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 pin numbers in numerical sequence name pin # type definition vdd 1 3.3v gnd 2 clkrtci 3 i rtc crystal oscillator input, 32khz clkrtco 4 o rtc crystal output gnd 5 dq0 6 i/o dram data bit 0, pull high/low, mapping to register dram_type[0] dq1 7 i/o dram data bit 1, pull high/low, mapping to register dram_type[1] dq2 8 i/o dram data bit 2, pull high/low, mapping to register dck[0] dq3 9 i/o dram data bit 3, pull high/low, mapping to register dck[1] dq4 10 i/o dram data bit 4, , pull high/low, mapping to register dck[2] dq5 11 i/o dram data bit 5, pull high/low, mapping to register dck[3] dq6 12 i/o dram data bit 6, pull high/low, mapping to register test[0] dq7 13 i/o dram data bit 7, pull high/low, mapping to register test[1] vdd 14 3.3v gnd 15 dq15 16 i/o dram data bit 15, pull high/low, mapping to register test[9] dq14 17 i/o dram data bit 14, pull high/low, mapping to register test[8] dq13 18 i/o dram data bit 13, pull high/low, mapping to register test[7] dq12 19 i/o dram data bit 12, pull high/low, mapping to register test[6] dq11 20 i/o dram data bit 11, pull high/low, mapping to register test[5] dq10 21 i/o dram data bit 10, pull high/low, mapping to register test[4] dq9 22 i/o dram data bit 9, pull high/low, mapping to register test[3] dq8 23 i/o dram data bit 8, pull high/low, mapping to register test[2] dwe_b 24 o dram write enable dcas_b 25 o dram column address strobe dras_b 26 o dram row address strobe sdcsa_b 27 o sdram #0 chip select sdcsb_b 28 o sdram #1 chip select sdcke 29 o sdram clock enable vdd 30 3.3v sdclko 31 o sdram clock output gnd 32 doe_b 33 o sdram, ldqm, udqm, edoram output enable dbank 34 o sdram bank select da10 35 o sdram address bit 10 da0 36 o dram address bit 0 da1 37 o dram address bit 1 da2 38 o dram address bit 2
4 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 name pin # type definition da3 39 o dram address bit 3 da9 40 o sdram address bit 9 da8 41 o dram address bit 8 da7 42 o dram address bit 7 da6 43 o dram address bit 6 da5 44 o dram address bit 5 da4 45 o dram address bit 4 fwp_b 46 o flash memory write protect fwe_b 47 o nand type flash memory write enable serial flash data output fale 48 o nand type flash memory address latch enable serial flash memory #3 chip select fcle 49 o nand type flash memory command latch enable serial flash memory #2 chip select frb_b 50 i nand type flash memory read/busy input serial flash data input fre_b 51 o nand type flash memory read enable serial flash clock output fcea_b 52 o flash memory #0 chip select fceb_b 53 o flash memory #1 chip select gnd 54 vdd 55 3.3v gnd 56 fq3 57 i/o nand type flash memory data bit 3, pull high/low, mapping to register gp_cfg[0] fq2 58 i/o nand type flash memory data bit 2, pull high/low, mapping to register flash_type[2] fq1 59 i/o nand type flash memory data bit 1, pull high/low, mapping to register flash_type[1] vdd 60 3.3v fq0 61 i/o nand type flash memory data bit 0, pull high/low, mapping to register flash_type[0] fq4 62 i/o nand type flash memory data bit 4, pull high/low, mapping to register gp_cfg[1] fq5 63 i/o nand type flash memory data bit 5, pull high/low, mapping to register gp_cfg[2] fq6 64 i/o nand type flash memory data bit 6, pull high/low, mapping to register gp_cfg[3] fq7 65 i/o nand type flash memory data bit 7, pull high/low, mapping to register gp_cfg[4] rg 66 o reset gate pulse output for ccd image sensor h1 67 o horizontal transfer pulse output 1 for ccd image sensor h2 68 o horizontal transfer pulse output 2 for ccd image sensor xsub 69 o pulse output for electronic shutter xv0/ 70 i/o vertical transfer-pulse 0 for ccd image sensor; also can be programmed to vertical fri sync signal input. xv1/ 71 i/o vertical transfer-pulse 1 for ccd image sensor; also can be programmed to hri horizontal sync signal input.
5 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 name pin # type definition xv2/ 72 o vertical transfer pulse 2 for ccd image sensor; also can be programmed to vertical fro sync signal output xv3/ 73 o vertical transfer pulse 3 for ccd image sensor; also can be programmed to hro horizontal sync signal output xsg1 74 o readout pulse 1 for ccd image sensor xsg2 75 o readout pulse 2 for ccd image sensor xshp 76 o pre-charge level sample-and-hold pulse xshd 77 o data level sample-and-hold pulse gnd 78 xrs 79 o sample-and-hold pulse output for analog/digital conversion ic xclpdm 80 o dummy bit block clamp pulse output xclpob 81 o optical black bit block clamp pulse output pblk 82 o pre-blanking pulse that corresponds to the cease period of horizontal transfer pulse for ccd image sensor. vdd 83 3.3v adck 84 o clock output for analog/digital conversion ic or cmos image sensor. sd0 85 i sensor input data bit 0 (lsb) sd1 86 i sensor input data bit 1 sd2 87 i sensor input data bit 2 sd3 88 i sensor input data bit 3 sd4 89 i sensor input data bit 4 sd5 90 i sensor input data bit 5 sd6 91 i sensor input data bit 6 sd7 92 i sensor input data bit 7 sd8 93 i sensor input data bit 8 sd9 94 i sensor input data bit 9(msb) vdd 95 3.3v gnd 96 gpio 12 97 i/o gpio bit 12 gpio 13 98 i/o gpio bit 13 gpio 14 99 i/o gpio bit 14 gpio 15 100 i/o gpio bit 15 gpio 16 101 i/o gpio bit 16 gnd 102 gpio 17 103 i/o gpio bit 17 gpio 18 104 i/o gpio bit 18 gpio 19 105 i/o gpio bit 19 gpio 20 106 i/o gpio bit 20, 8051 clock off output clksni 107 i sensor clock crystal oscillator input clksno 108 o sensor clock crystal output
6 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 name pin # type definition gpio 21 109 i/o gpio bit 21, flash light strobe output gpio 22 110 i/o gpio bit 22 gpio 23 111 i/o gpio bit 23 gpio 24 112 i/o gpio bit 24 gpio 25 113 i/o gpio bit 25 vdd 114 3.3v clk48i 115 i system clock crystal oscillator input, 48mhz clk48o 116 o system clock crystal output ea 117 i external rom enable rst_b 118 i hardware reset pale 119 i/o address latch enable psen_b 120 i/o program strobe enable p0.0 121 i/o 8051 port 0 bit 0, external address/data bus bit 0 p0.1 122 i/o 8051 port 0 bit 1, external address/data bus bit 1 p0.2 123 i/o 8051 port 0 bit 2, external address/data bus bit 2 p0.3 124 i/o 8051 port 0 bit 3, external address/data bus bit 3 p0.4 125 i/o 8051 port 0 bit 4, external address/data bus bit 4 p0.5 126 i/o 8051 port 0 bit 5, external address/data bus bit 5 p0.6 127 i/o 8051 port 0 bit 6, external address/data bus bit 6 gnd 128 p0.7 129 i/o 8051 port 0 bit 7, external address/data bus bit 7 p1.0 130 i/o 8051 port 1 bit 0, gpio bit 0, p1.1 131 i/o 8051 port 1 bit 1, gpio bit 1, p1.2 132 i/o 8051 port 1 bit 2, gpio bit 2, p1.3 133 i/o 8051 port 1 bit 3, gpio bit 3 p1.4 134 i/o 8051 port 1 bit 4, gpio bit 4 p1.5 135 i/o 8051 port 1 bit 5, gpio bit 5 p1.6 136 i/o 8051 port 1 bit 6, gpio bit 6, scl p1.7 137 i/o 8051 port 1 bit 7, gpio bit 7, sda p2.0 138 i/o 8051 port 2 bit 0, external address bus bit 8 p2.1 139 i/o 8051 port 2 bit 1, external address bus bit 9 p2.2 140 i/o 8051 port 2 bit 2, external address bus bit 10 gnd 141 vdd 142 3.3v p2.3 143 i/o 8051 port 2 bit 3, external address bus bit 11 p2.4 144 i/o 8051 port 2 bit 4, external address bus bit 12 p2.5 145 i/o 8051 port 2 bit 5, external address bus bit 13 p2.6 146 i/o 8051 port 2 bit 6, external address bus bit 14 p2.7 147 i/o 8051 port 2 bit 7, external address bus bit 15 p3.0 148 i/o 8051 port 3 bit 0, gpio bit 8, rxd p3.1 149 i/o 8051 port 3 bit 1, gpio bit 9, txd
7 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 name pin # type definition p3.2 150 i/o 8051 port 3 bit 2, interrupt 0, p3.3 151 i/o 8051 port 3 bit 3, interrupt 1, p3.4 152 i/o 8051 port 3 bit 4, gpio bit 10 p3.5 153 i/o 8051 port 3 bit 5, gpio bit 11 p3.6 154 i/o 8051 port 3 bit 6, external sram write strobe, gpio26 p3.7 155 i/o 8051 port 3 bit 7, external sram read strobe, gpio27 gnd 156 uvdd 157 3.3v d+ 158 i/o data+, usb data bus d- 159 i/o data-, usb data bus ugnd 160 pin numbers/definition by function power supply name pin # type definition vdd 1 3.3v vdd 14 3.3v vdd 30 3.3v vdd 55 3.3v vdd 60 3.3v vdd 83 3.3v vdd 95 3.3v vdd 114 3.3v vdd 142 3.3v uvdd 61 3.3v gnd 2 gnd 5 gnd 15 gnd 32 gnd 54 gnd 56 gnd 78 gnd 96 gnd 102 gnd 128 gnd 141 gnd 156 ugnd 62
8 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 sensor interface name pin # type definition rg 66 o reset gate pulse output for ccd image sensor h1 67 o horizontal transfer pulse output 1 for ccd image sensor h2 68 o horizontal transfer pulse output 2 for ccd image sensor xsub 69 o pulse output for electronic shutter xv0/ 70 i/o vertical transfer-pulse 0 for ccd image sensor; also can be programmed to vertical fri sync signal input. xv1/ 71 i/o vertical transfer-pulse 1 for ccd image sensor; also can be programmed to horizontal hri sync signal input. xv2/ 72 o vertical transfer pulse 2 for ccd image sensor; also can be programmed to vertical fro sync signal input xv3/ 73 o vertical transfer pulse 3 for ccd image sensor; also can be programmed to horizontal hro sync signal input xsg1 74 o readout pulse 1 for ccd image sensor xsg2 75 o readout pulse 2 for ccd image sensor xshp 76 o pre-charge level sample-and-hold pulse xshd 77 o data level sample-and-hold pulse xrs 79 o sample-and-hold pulse output for analog/digital conversion ic xclpdm 80 o dummy bit block clamp pulse output xclpob 81 o optical black bit block clamp pulse output pblk 82 o pre-blanking pulse that corresponds to the cease period of horizontal transfer pulse for ccd image sensor. adck 84 o clock output for analog/digital conversion ic or cmos image sensor. phase adjustment in 90 o units. sd0 85 i sensor input data bit 0 (lsb) sd1 86 i sensor input data bit 1 sd2 87 i sensor input data bit 2 sd3 88 i sensor input data bit 3 sd4 89 i sensor input data bit 4 sd5 90 i sensor input data bit 5 sd6 91 i sensor input data bit 6 sd7 92 i sensor input data bit 7 sd8 93 i sensor input data bit 8 sd9 94 i sensor input data bit 9(msb)
9 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 dram interface name pin # type definition dq0 6 i/o dram data bit 0, pull high/low, mapping to register dram_type[0] dq1 7 i/o dram data bit 1, pull high/low, mapping to register dram_type[1] dq2 8 i/o dram data bit 2, pull high/low, mapping to register dck[0] dq3 9 i/o dram data bit 3, pull high/low, mapping to register dck[1] dq4 10 i/o dram data bit 4, pull high/low, mapping to register dck[2] dq5 11 i/o dram data bit 5, pull high/low, mapping to register dck[3], dq6 12 i/o dram data bit 6, pull high/low, mapping to register test[0] dq7 13 i/o dram data bit 7, pull high/low, mapping to register test[1] dq8 23 i/o dram data bit 8, pull high/low, mapping to register test[2] dq9 22 i/o dram data bit 9, pull high/low, mapping to register test[3] dq10 21 i/o dram data bit 10, pull high/low, mapping to register test[4] dq11 20 i/o dram data bit 11, pull high/low, mapping to register test[5] dq12 19 i/o dram data bit 12, pull high/low, mapping to register test[6] dq13 18 i/o dram data bit 13, pull high/low, mapping to register test[7] dq14 17 i/o dram data bit 14, pull high/low, mapping to register test[8] dq15 16 i/o dram data bit 15, pull high/low, mapping to register test[9] dwe_b 24 o dram write enable dcas_b 25 o dram column address strobe dras_b 26 o dram row address strobe sdcsa_b 27 o sdram #0 chip select sdcsb_b 28 o sdram #1 chip select sdcke 29 o sdram clock enable sdclko 31 o sdram clock output doe_b 33 o sdram, ldqm, udqm,edoram output enable da0 36 o dram address bit 0 da1 37 o dram address bit 1 da2 38 o dram address bit 2 da3 39 o dram address bit 3 da4 45 o dram address bit 4 da5 44 o dram address bit 5 da6 43 o dram address bit 6 da7 42 o dram address bit 7 da8 41 o dram address bit 8 da9 40 o sdram address bit 9 da10 35 o sdram address bit 10 dbank 34 o sdram bank select
10 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 flash memory interface name pin # type definition fcle 49 o nand type flash memory command latch enable serial flash memory #2 chip select fale 48 o nand type flash memory address latch enable serial flash memory #3 chip select fwe_b 47 o nand type flash memory write enable serial flash memory data output fwp_b 46 o flash memory write protect frb_b 50 i nand type flash memory read/busy input serial flash memory data input fre_b 51 o nand type flash memory read enable serial flash memory clock output fcea_b 52 o flash memory #0 chip select fceb_b 53 o flash memory #1 chip select fq0 61 i/o nand type flash memory data bit 0, pull high/low, mapping to register flash_type[0] fq1 59 i/o nand type flash memory data bit 1, pull high/low, mapping to register flash_type[1] fq2 58 i/o nand type flash memory data bit 2, pull high/low, mapping to register flash_type[2] fq3 57 i/o nand type flash memory data bit 3, pull high/low, mapping to register gp_cfg[0] fq4 62 i/o nand type flash memory data bit 4, pull high/low, mapping to register gp_cfg[1] fq5 63 i/o nand type flash memory data bit 5, pull high/low, mapping to register gp_cfg[2] fq6 64 i/o nand type flash memory data bit 6, pull high/low, mapping to register gp_cfg[3] fq7 65 i/o nand type flash memory data bit 7, pull high/low, mapping to register gp_cfg[4] usb interface name pin # type definition d+ 158 i/o data+, usb data bus d- 159 i/o data-, usb data bus micro-controller interface name pin # type definition p0.0 121 i/o 8051 port 0 bit 0, external address/data bus bit 0 p0.1 122 i/o 8051 port 0 bit 1, external address/data bus bit 1 p0.2 123 i/o 8051 port 0 bit 2, external address/data bus bit 2 p0.3 124 i/o 8051 port 0 bit 3, external address/data bus bit 3 p0.4 125 i/o 8051 port 0 bit 4, external address/data bus bit 4 p0.5 126 i/o 8051 port 0 bit 5, external address/data bus bit 5 p0.6 127 i/o 8051 port 0 bit 6, external address/data bus bit 6 p0.7 129 i/o 8051 port 0 bit 7, external address/data bus bit 7 p1.0 130 i/o 8051 port 1 bit 0, gpio bit 0, p1.1 131 i/o 8051 port 1 bit 1, gpio bit 1, p1.2 132 i/o 8051 port 1 bit 2, gpio bit 2, p1.3 133 i/o 8051 port 1 bit 3, gpio bit 3
11 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 p1.4 134 i/o 8051 port 1 bit 4, gpio bit 4 p1.5 135 i/o 8051 port 1 bit 5, gpio bit 5 p1.6 136 i/o 8051 port 1 bit 6, gpio bit 6, scl p1.7 137 i/o 8051 port 1 bit 7, gpio bit 7, sda p2.0 138 i/o 8051 port 2 bit 0, external address bus bit 8 p2.1 139 i/o 8051 port 2 bit 1, external address bus bit 9 p2.2 140 i/o 8051 port 2 bit 2, external address bus bit 10 p2.3 143 i/o 8051 port 2 bit 3, external address bus bit 11 p2.4 144 i/o 8051 port 2 bit 4, external address bus bit 12 p2.5 145 i/o 8051 port 2 bit 5, external address bus bit 13 p2.6 146 i/o 8051 port 2 bit 6, external address bus bit 14 p2.7 147 i/o 8051 port 2 bit 7, external address bus bit 15 p3.0 148 i/o 8051 port 3 bit 0, gpio bit 8, rxd p3.1 149 i/o 8051 port 3 bit 1, gpio bit 9, txd p3.2 150 i/o 8051 port 3 bit 2, interrupt 0, p3.3 151 i/o 8051 port 3 bit 3, interrupt 1, p3.4 152 i/o 8051 port 3 bit 4, gpio bit 10 p3.5 153 i/o 8051 port 3 bit 5, gpio bit 11 p3.6 154 i/o 8051 port 3 bit 6, external sram write strobe, gpio26 p3.7 155 i/o 8051 port 3 bit 7, external sram read strobe, gpio27 ea 117 i external rom enable pale 119 i/o address latch enable psen_b 120 i/o program strobe enable miscellaneous name pin # type definition gpio12 97 i/o gpio bit 12, sel_sram_b gpio 13 98 i/o gpio bit 13, usb_dpluso gpio 14 99 i/o gpio bit 14, usb_dminuso gpio 15 100 i/o gpio bit 15, usb_data_en_b gpio 16 101 i/o gpio bit 16, usb_suspendo gpio 17 103 i/o gpio bit 17, usb_dplusi gpio 18 104 i/o gpio bit 18, usb_dmiusi gpio 19 105 i/o gpio bit 19, usb_datai gpio 20 106 i/o gpio bit 20, 8032 clock off output gpio 21 109 i/o gpio bit 21, flash light strobe output gpio 22 110 i/o gpio bit 22 gpio 23 111 i/o gpio bit 23 gpio 24 112 i/o gpio bit 24
12 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 absolute maximum ratings rating v alue dc supply voltage(vcc) 3.0v to 3.6v dc input/output voltage(vin/vout) -0.5v to vcc+0.5v ambient temperature(ta) 0 to 70celsius storage temperature(tstg) -40 to 125celsius esd rating(rzap=1.5k,czap=100pf) 2000v power dissipation(pd) 0.7mw power dissipation(normal) 0.4w dc characteristics symbol description min max test conditions unit vil input low voltage - 0.8 volt vih input high voltage 2.0 - volt vol output low voltage - 0.4 i=4ma volt voh output low voltage 0.8vcc - i=4ma volt icc power supply current - 130 vcc=3.3v 640x480x10hz ma iil input low current -1 1 vcc=3.5v, vin=0v ua iih input high current - 1 vin=vcc ua rpullup pull up resistance 20 60 k ohm idd static idd current - ma cin input capacitance 3 10 pf cout output capacitance 45 pf ac characteristics reset timing ac characteristics rst_b trst symbol description min max test conditions unit trst reset pulse width 250 ns
13 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 clock ac characteristics tcyc thigh tlow symbol parameter min max unit 1/tcyc typ clk48i mhz 10.4 48 15.2 10.4 10.4 15.2 10.4 clk32ki 32.768 khz thigh tlow clk48i clk32ki clk48i clk32ki ns ms ns ms sd_clk sd_clk sd_clk ns ns 48 mhz
14 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 sdram interface timings sdcke sdcs*_b da dq sd_clk dras_b dcas_b dwe_b doe_b tcks tckh tcms tas tah tcmh tcms tcms tcmh tcmh tds tdh parameter min symbol typ max unit address setup time address hold time data-in setup time data-in hold time cke setup time cke hold time command setup time command hold time tas tah tds tdh tcks tckh tcms tcmh ns ns ns ns ns ns ns ns 3 1.5 3 1.5 3 1.5 3 1.5 __ __ __ __ __ __ __ __ note : sdram interface timing is adjustable in the step of about 2ns
15 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 * command latch cycle fce*_b fwe_b fcle fale fq 0 ~ 7 command * address latch cycle fce*_b fwe_b fcle fale fq 0 ~ 7 a 0 ~a 7 a 8 ~a 15 a 16 ~a 20 t cls t clh t ch t alh t wp t als t ds t dh t cs t cls t cs t wc t wc t wp t wh t wp t wh t als t ds t dh t dh t ds t dh t alh t wp t ds nandflash interface timings
16 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 * input data latch cycle fce*_b fcle fwe_b fq 0 ~ 7 din 0 din 1 din 255 fale t clh t ch t als t wc t wp t wh t wp t ds t dh t ds t dh t ds t dh t wp * sequential out cycle after read (cle=l, we =h, ale=l) fre_b fce*_b frb_b fq 0 ~ 7 dout dout dout t rc t rr t chz* t rhz* t reh ? ? ?
17 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 * status read cycle fce*_b fwe_b fcle fre_b fq 0 ~ 7 70h status output t cls t clh t cls t cs t wp t ch t whr t chz* t rhz* t dh t ds
18 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time tcls 1 clk * cle hold time tclh 2 clk ce setup time tcs 2 clk ce hold time tch 8 clk we pulse width twp 2 clk ale setup time tals 1 clk ale hold time talh 2 clk data setup time tds 2 clk data hold time tdh 2 clk write cycle time twc 4 clk we high hold time twh 2 clk ac characteristics for operation parameter symbol min max unit ready to re low trr 6 clk read cycle time trc 4 clk re high to output hi-z trhz 0 ce high to output hi-z tchz 0 re high hold time treh 1 clk we high to re low twhr 3 clk * 1 clk = one clk48i cycle time
19 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 sensor interface timings adck sd[9:0] hro tpd1 tpd2 tadck tsd symbol definition min. typ. max. unit tadck adck cycle time 20.8 - - ns tsd sensor data cycle time 1 - 6 tadck tpd1 sensor data input delay 0 - 6 tadck tpd2 hro rising delay 0 - - ns * 1 tadck = one adck cycle time
20 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 ccd sensor interface timings clk48i h1/h2 rg xrs xshp xshd tpd3 twh1 tpd4 twh2 tpd5 twh3 tpd6 twl1 tpd7 twl2 tck th1 cload : 35pf, 25 o c symbol definition min. typ. max. unit th1 h1/h2 cycle time 4 - - sclk* tpd3 h1/h2 rising delay, activated by the rising edge of clk48i 1.2 - - ns** tpd4 rg rising delay, activated by the rising edge of clk48i 3.0 - - ns** tpd5 xrs rising delay, activated by the rising edge of clk48i 3.0 - - ns** tpd6 xshp falling delay, activated by the rising edge of clk48i 3.0 - - ns** tpd7 xshd falling delay, activated by the rising edge of clk48i 2.6 - - ns** twh1 h1/h2 high level width 2 - sclk twh2 pulse width of rg 1 sclk twh3 pulse width of xrs 1 sclk twl1 pulse width of xshp 1 - sclk twl2 pulse width of xshd 1 sclk * 1 sclk = one cycle of clk48i or sd.clk ** adjustable by registry settings
21 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 0.9vdd 0.9vdd 0.9vdd 0.9vdd 0.1vdd 0.1vdd 0.1vdd 0.1vdd trh1 tfh1 tfrg trrg h1 rg symbol definition min. typ. max. unit trh1 h1 rise time 2.1 ns tfh1 h1 fall time 1.8 ns trrg rg rise time 2.1 ns tfrg rg fall time 1.8 ns cload : 30pf, 25 o c
22 rev. 2.5b, aug. 18, 2000 p/n: pm0743 MX88L60 package information scale unit title macronix international co., ltd. ???1qla?|3--?q drawn approved tolerance revision dwg. no. 6110-0239 1 160 lqfp 20x20x1.4mm(2.0mm footprint)package c.l.chiang jw lin outline dimensions for -
MX88L60 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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